Generally, low voltage differential signaling (LVDS) is used for high-speed data transport between a transmitter (for example, a timing controller) and a receiver (for example, a panel) in a display apparatus. The LVDS reduces power consumption when the transmitter transmits data and enables high-speed transmission and, therefore, is advantageous in terms of low power, high-speed operation, noise, and cost. For this reason, the LVDS is used as a standard in data communication.
For instance, when a first power supply voltage is 2.5 V in the interface between a transmitter and a receiver in the LVDS system, the transmitter can transmit data of “1” with 1.4 V and data of “0” with 1.0 V. In other words, the amount of change between the data “1” and the data “0” is only 0.4 V. Accordingly, the LVDS system responds to signal changes more quickly than another method (for example, single-ended signaling) in which the amount of change is determined by a single reference voltage (for example, a ground voltage) and thereby is advantageous in high-speed operation. In addition, since signals are differentially transmitted in the LVDS system, common mode noise is suppressed and, thus, adverse influence of noise is alleviated.
In a display apparatus using LVDS, a data, transmission rate is limited by the switching speed of the transmitter and the receiver and the bandwidth of the transmission line. More specifically, an interface for large flat screen displays uses a long transmission, line and has a low bandwidth. In order to increase a transmission rate of the transmission line having the low bandwidth, amplitude modulation has recently been used.
FIG. 1 is a waveform diagram for explaining amplitude modulation in conventional LVDS. Referring to FIG. 1, conventional LVDS transmits two bits at a time using amplitude modulation (for example, pulse amplitude modulation (PAM)), thereby doubling a transmission rate. In other words, in the conventional data receiving method, two bits are simultaneously transmitted using four symbols (that is, 00, 01, 11, and 10) according to a symbol state of the amplitude modulated signals while the frequency of a transmission signal is maintained constant in a transmission line having a limited bandwidth and, therefore, a higher transmission rate is accomplished.
FIG, 2 is a functional block diagram of a conventional data receiver 10, FIG. 3 is a circuit diagram of a first amplifier used in the receiver shown in FIG. 2, FIG. 4 is a circuit diagram of a second amplifier used in the receiver shown in FIG, 2, Referring to FIGS. 1 through 4, the data receiver 10 includes a first comparator 11, a first latch 13, a first amplifier 15, a second comparator 17, a second amplifier 19, a third comparator 21, an XOR gate 23, and a second latch 25.
The first comparator 11 receives and compares first and second amplitude modulated differential input signals Vin+ and Vin− and outputs a result of the comparison as a first bit Vcom1+. For instance, when the first input signal Vin+ is greater than the second input signal Vin−, the first comparator 11 outputs the first bit Vcom1+ at a first logic level (for example, a high level of “1”). When the first input signal Vin+ is less than the second input signal Vin−, the first comparator 11 outputs the first bit Vcom1+ at a second logic level (for example, a low level of “0”).
The first bit Vcom1+ output from the first comparator 11 is a first bit for example, a most significant bit (MSB), of two bits output from the data receiver 10. The first latch 13 latches the first bit Vcom1+ based on a clock signal CLK fed thereto and outputs a latched signal Vout1 as the first bit of the two bits output from the data receiver 10.
As shown in FIG. 3, the first amplifier 15 includes a pair of first transistors P1 and P3 and a pair of second transistors P5 and P7. Output terminals of the first transistors P1 and P3 are respectively connected with output terminals of the second transistors P5 and P7.
The pair of first transistors P1 and P3 amplify a difference between the first input signal Vin+ and the second input signal Vin− based on a first current 11 and the pair of second transistors P5 and P7 amplify a difference between a first reference signal VrefH and a second reference signal VrefL based on the first current 11. In other words, the first amplifier 15 outputs differential output signals Vp1+ and Vp1− that have a difference corresponding to the sum of the output of the pair of the first transistors P1 and P3 and the output of the pair of the second transistors P5 and P7.
The second comparator 17 receives and compares the differential output signals Vp1+ and Vp1− output from die first amplifier 15 and outputs a first comparison signal Vcom2+. For instance, when the first differential output signal Vp1+ is greater than the second differential output signal Vp1−, the second comparator 17 outputs the first comparison signal Vcom2+ at a first, logic level, for example, a high level of “1”. When the first differential output signal Vp1+ is less than the second differential output signal Vp1−, the second comparator 17 outputs the first comparison signal Vcom2+ at a second logic level, for example, a low level of “0”. In other words, the second comparator 17 can compare a difference between the differential input signals Vin+ and Vin− (that is, Vin+-Vin−) with a difference between the reference signals VrefL and VrefH (that is, VrefH-VrefL) by comparing the first and second differential output signals Vp1+ and Vp1−.
As shown, in FIG. 4, the second amplifier 19 includes a pair of third transistors P9 and P11 and a pair of fourth transistors P13 and P15. Output terminals of the third transistors P9 and P11 are respectively connected with output; terminals of the fourth transistors P13 and P15. The second amplifier 19 has almost the same circuit structure and operations as the first amplifier 15, with the exception that reference signals respectively input to the fourth transistors P13 and P15 respectively have opposite phases to the reference signals respectively input to the second transistors P5 and P7. Thus, detailed descriptions thereof will be omitted.
The third comparator 21 has almost the same circuit structure and operations as the second comparator 17. Thus, detailed descriptions thereof will be omitted. In other words, the third comparator 21 can compare the difference between the differential input signals Vin+ and Vin− (that is, Vin+-Vin−) with the difference between the reference signals VrefL and VrefH ( that is, VrefH-VrefL) by comparing third and fourth differential output signals Vp2+ and Vp2−.
The XOR gate 23 performs an XOR operation on the first comparison signal Vcom2+ received from the second comparator 17 and a second comparison signal Vcom3+ received from the third comparator 21. In other words, the XOR gate 23 outputs an output signal V1 at a first logic level (for example, a high level of “1”) when “second reference signal VrefL—first reference signal VrefH”<“first differential input signal Vin+—second differential input signal Vin−”<“first reference signal VrefH—second reference signal VrefL” and outputs the output signal V1 at a second logic level (for example, a low level of “0”) when “second reference signal VrefL—first reference signal VrefH”>“first differential input signal Vin+—second differential input signal Vin−” or “first differential input signal Vin+—second differential input signal Vin−”>“first reference signal VrefH—second reference signal VrefL”.
The second latch 25 latches the output signal V1 from the XOR gate 23 based on the clock signal CLK fed thereto and outputs a latched, signal Vout2 as a second bit (for example, a least significant bit (LSB)) of the two bits output from the data receiver 10.
The conventional data receiver 10, however, requires a plurality of amplifiers 15 and 19 and a plurality of comparators 17 and 21 in order to output the first bit Vout1 and also requires a separate reference signal generator (not shown) in order to generate the reference signals VrefL and VrefH input to the amplifiers 15 and 19. As a result, the many circuits implemented in the data receiver 10 may cause a chip size to increase, thereby increasing power consumption.